Allwinner A20 - AC97 Interface Special Requirement

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 738 / 812
6.10.8. AC97 Interface Special Requirement
6.10.8.1. PIN LIST
Port Name
Width
Direction
Description
AC_BIT_CLK
1
IN
Digital Audio Serial Clock provided by Codec
AC_SYNC
1
OUT
Digital Audio Sample rate/sync
AC_MCLK
1
OUT
AC97 Codec Input Mclk
AC_SDATA_IN
1
IN
Digital Audio serial Data Input
AC_SDTA_OUT
1
OUT
Digital Audio serial Data Output
Note:BIT_CLK is provided by AC97 Codec.
6.10.8.2. AC97 CLOCK REQUIREMENT
Clock Name
Description
Requirement
apb_clk
APB bus clock
s_clk
AC97 serial access x1
clock
24.576 MHz or 22.5792 MHz from CCU