Allwinner A20 - LRADC Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 192 / 812
Register Name
Offset
Description
LRADC_CTRL
0x00
LRADC Control Register
LRADC_INTC
0x04
LRADC Interrupt Control Register
LRADC_INTS
0x08
LRADC Interrupt Status Register
LRADC_DATA0
0x0c
LRADC Data Register 0
LRADC_DATA1
0x10
LRADC Data Register 1
1.14.4. LRADC Register Description
1.14.4.1. LRADC CONTROL REGISTER
Offset: 0x00
Register Name: LRADC_CTRL
Bit
Read/
Write
Default/H
ex
Description
31: 24
R/W
0x1
FIRST_CONCERT_DLY.
ADC First Convert Delay setting, ADC conversion is delayed by n
samples
23:22
R/W
0x0
ADC_CHAN_SELECT.
ADC channel select
00: ADC0 channel
01: ADC1 channel
1x: ADC0&ADC1 channel
21:20
/
/
/
19:16
R/W
0x0
CONTINUE_TIME_SELECT.
Continue Mode time select, one of 8*(N+1) sample as a valuable
sample data
15:14
/
/
/
13:12
R/W
0x0
KEY_MODE_SELECT.
Key Mode Select:
00: Normal Mode
01: Single Mode
10: Continue Mode
11:8
R/W
0x1
LEVELA_B_CNT.