Allwinner A20 - Page 193

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 193 / 812
Offset: 0x00
Register Name: LRADC_CTRL
Bit
Read/
Write
Default/H
ex
Description
Level A to Level B time threshold select, judge ADC convert value
in level A to level B in n+1 samples
7
/
/
/
6
R/W
0x1
LRADC_HOLD_EN.
LRADC Sample hold Enable
0: Disable
1: Enable
5: 4
R/W
0x2
LEVELB_VOL.
Level B Corresponding Data Value setting (the real voltage value)
00: 0x3C (~1.9v)
01: 0x39 (~1.8v)
10: 0x36 (~1.7v)
11: 0x33 (~1.6v)
3: 2
R/W
0x2
LRADC_SAMPLE_RATE.
LRADC Sample Rate
00: 250 Hz
01: 125 Hz
10: 62.5 Hz
11: 32.25 Hz
1
/
/
/
0
R/W
0x0
LRADC_EN.
LRADC enable
0: Disable
1: Enable
1.14.4.2. LRADC INTERRUPT CONTROL REGISTER
Offset: 0x04
Register Name: LRADC_INTC
Bit
Read/
Write
Default/He
x
Description
31:16
/
/
/
12
R/W
0x0
ADC1_KEYUP_IRQ_EN.
ADC 1 Key Up IRQ Enable
0: Disable