Allwinner A20 - 6.1. SD;MMC

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6.1. SD/MMC

6.1.1. Overview

The SD/MMC controller can be configured as a Secure Digital Multimedia Card controller, which

simultaneously supports Secure Digital memory (SD Memo), UHS-1 Card, Secure Digital I/O (SDIO),

Multimedia Cards (MMC), eMMC Card and Consumer Electronics Advanced Transport Architecture

(CE-ATA).

It features:

 Support industry-standard AMBA High-Performance Bus (AHB) and it is fully compliant with the AMBA

Specification, Revision 2.0. Supports 32-bit Little Endean bus.

 Support AMBA AHB Slave mode

 Support Secure Digital memory protocol commands (up to SD3.0)

 Support Secure Digital I/O protocol commands

 Support Multimedia Card protocol commands (up to MMC4.3)

 Support CE-ATA digital protocol commands

 Support eMMC boot operation and alternative boot operation

 Support Command Completion signal and interrupt to host processor and Command Completion

Signal disable feature

 Support one SD (Verson1.0 to 3.0) or MMC (Verson3.3 to 4.3) or CE-ATA device

 Support hardware CRC generation and error detection

 Support programmable baud rate

 Support host pull-up control

 Support SDIO interrupts in 1-bit and 4-bit modes

 Support SDIO suspend and resume operation

 Support SDIO read wait

 Support block size of 1 to 65535 bytes

 Support descriptor-based internal DMA controller

 Internal 32x32-bit (128 bytes total) FIFO for data transfer

6.1.2. SD/MMC Timing Diagram

Please refer to related specifications:

 Physical Layer Specification Ver3.00 Final, 2009.04.16

 SDIO Specification Ver2.00

 Consumer Electronics Advanced Transport Architecture (CE-ATA – version 1.1)

 Multimedia Cards (MMC – version 4.2)

 JEDEC Standard – JESD84-44, Embedded Multimedia Card (eMMC) Card Product Standard