Allwinner A20 - DEFE Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 482 / 812
Register Name
Offset
Description
Transition Improve Configuration Register
DEFE_VPP_LP1_REG
0x0A08
DEFE Video Post Process Luminance
Peaking Configuration 1 Register
DEFE_VPP_LP2_REG
0x0A0C
DEFE Video Post Process Luminance
Peaking Configuraion 2 Register
DEFE_VPP_WLE_REG
0x0A10
DEFE Video Post Process White Level
Extension Configuration Register
DEFE_VPP_BLE_REG
0x0A14
DEFE Video Post Process Black Level
Extension Configuration Register
5.3.4. DEFE Register Description
5.3.4.1. DEFE_EN_REG
Offset: 0x0
Register Name: DEFE_EN_REG
Bit
Read/
Write
Default/
Hex
Description
31:1
/
/
/
0
R/W
0x0
EN
DEFE enable
0: Disable
1: Enable
When DEFE enable bit is disabled, the clock of DEFE module will
be disabled
If this bit is transition from 0 to 1, the frame process control
register and the interrupt enable register will be initialed to default
value, and the state machine of the module is reset
5.3.4.2. DEFE_FRM_CTRL_REG
Offset: 0x4
Register Name: DEFE_FRM_CTRL_REG
Bit
Read/
Write
Default/H
ex
Description
31:17
/
/
/