Allwinner A20 - CCU Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 38 / 812
Register Name
Offset
Description
HDMI_CLK_REG.
0x0150
HDMI CLOCK REGISTER
MALI400_CLK_REG
0x0154
MALI 400 CLOCK REGISTER
MBUS_SCLK_CFG_REG
0x015C
MBUS CLOCK CONFIGURATION
REGISTER
GMAC_CLK_REG
0x0164
GMAC CLOCK REGISTER
HDMI1_RST_REG
0x0170
HDMI1 RESET REGISTER
HDMI1_CTRL_REG
0x0174
HDMI1 CONTROL REGISTER
HDMI1_SLOW_CLK_REG
0x0178
HDMI1 SLOW CLOCK REGISTER
HDMI1_REPEAT_CLK_REG
0x017C
HDMI1 REPEAT CLOCK REGISTER
CLK_OUTA_REG
0x01F0
CLK OUTA
CLK_OUTB_REG
0x01F4
CLK OUTB
1.5.4. CCU Register Description
1.5.4.1. PLL1-CORE(DEFAULT: 0X21005000)
Offset: 0x00
Register Name: PLL1_CFG_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
PLL1_Enable.
0: Disable, 1: Enable.
The PLL1 output=(24MHz*N*K)/(M*P).
The PLL1 output is for the CORECLK.
Note: the output 24MHz*N*K clock
must be in the range of 240MHz~2GHz if the bypass is
disabled.
Its default is 384MHz.
30
/
/
/
29:26
/-
/
/
25
R/W
0x0
EXG_MODE.
Exchange mode.
24:20
/
/
/
19:18
/
/
/