Allwinner A20 - Page 39

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 39 / 812
Offset: 0x00
Register Name: PLL1_CFG_REG
Bit
Read/
Write
Default/Hex
Description
17:16
R/W
0x0
PLL1_OUT_EXT_DIVP.
PLL1 Output external divider P.
The range is 1/2/4/8.
15:13
/
/
/
12:8
R/W
0x10
PLL1_FACTOR_N
PLL1 Factor N..
Factor=0, N=1;
Factor=1, N=1;
Factor=2, N=2
……
Factor=31,N=31
7:6
/
/
/
5:4
R/W
0x0
PLL1_FACTOR_K.
PLL1 Factor K.(K=Factor + 1 )
The range is from 1 to 4.
3
R/W
0x0
SIG_DELT_PAT_IN.
Sigma-delta pattern input.
2
R/W
0x0
SIG_DELT_PAT_EN.
Sigma-delta pattern enable.
1:0
R/W
0x0
PLL1_FACTOR_M.
PLL1 Factor M. (M=Factor + 1 )
The range is from 1 to 4.
1.5.4.2. PLL1-TUNING(DEFAULT: 0X0A101000)
Offset: 0x04
Register Name: PLL1_TUN_REG
Bit
Read/
Write
Default/Hex
Description
31:0
/
/
/
1.5.4.3. PLL2-AUDIO(DEFAULT: 0X08100010)
Offset: 0x08
Register Name: PLL2_CFG_REG