Allwinner A20 - Page 40

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 40 / 812
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
PLL2_Enable.
0: Disable, 1: Enable.
The PLL2 is for Audio.
PLL2 Output = 24MHz*N/PLL2_PRE_DIV/PLL2_POST_DIV.
1X = 48*N/PreDiv/PostDiv/2(not 50% duty)
2X = 48*N/PreDiv/4( 8X/4 50% duty)
4X = 48*N/PreDiv/2( 8X/2 50% duty )
8X = 48*N/PreDiv( not 50% duty)
30
/
/
/
29:26
R/W
0x2
PLL2_POST_DIV.
PLL2 post-dividor[3:0].
0000: 0x1
0001: 0x1
0010: 0x2
……
1111: 0xf
25:21
/
/
/
20:16
/
/
/
15
/
/
/
14:8
R/W
0x0
PLL2_Factor_N.
PLL2 Factor N.
Factor=0, N=1;
Factor=1, N=1;
……
Factor=0x7F, N=0x7F;
7:5
/
/
/
4:0
R/W
0x10
PLL2_PRE_DIV.
PLL2 pre-dividor[4:0].
PLL2_PRE_DIV=divider
00000: 0x1
00001: 0x1
……
11111: 0x1F