Allwinner A20 - Page 41

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 41 / 812
1.5.4.4. PLL2-TUNING(DEFAULT: 0X00000000)
Offset: 0x0C
Register Name: PLL2_TUN_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
SIG_DELT_PAT_EN.
Sigma-delta pattern enable.
30:29
R/W
0x0
SPR_FREQ_MODE.
Spread Frequency Mode.
00: DC=0
01: DC=1
10: Triangular
11: awmode
28:20
R/W
0x0
WAVE_STEP.
Wave step.
19
/
/
/
18:17
R/W
0x0
FREQ.
Frequency.
00: 31.5KHz
01: 32KHz
10: 32.5KHz
11: 33KHz
16:0
R/W
0x0
WAVE_BOT.
Wave Bottom.
1.5.4.5. PLL3-VIDEO 0(DEFAULT: 0X0010D063)
Offset: 0x10
Register Name: PLL3_CFG_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
PLL3_Enable.
0: Disable, 1: Enable.
In the integer mode, The PLL3 output=3MHz*M.
In the fractional mode, the PLL3 output is selected by bit 14.
The PLL3 output range is 27MHz~381MHz.
30:27
/
/
/
26:24
/
/
/