Allwinner A20 - Page 42

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 42 / 812
Offset: 0x10
Register Name: PLL3_CFG_REG
Bit
Read/
Write
Default/Hex
Description
23:21
/
/
/
20:16
/
/
/
15
R/W
0x1
PLL3_MODE_SEL.
PLL3 mode select.
0: fractional mode, 1: integer mode.
14
R/W
0x1
PLL3_FUNC_SET.
PLL3 fractional setting.
0: 270MHz, 1: 297MHz.
13
/
/
/
12:8
/
/
/
7
/
/
/
6:0
R/W
0x63
PLL3_FACTOR_M.
PLL3 Factor M.
The range is from 9 to 127.
1.5.4.6. PLL4-VE(DEFAULT: 0X21009911)
Offset: 0x18
Register Name: PLL4_CFG_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
PLL4_Enable.
0: Disable, 1: Enable.
The output = 24MHz*N*K
Note: the output 24MHz*N*K clock must be in the range of
240MHz~2GHz if the bypass is disabled.
30
R/W
0x0
PLL4_BYPASS_EN.
PLL4 Output Bypass Enable.
0: Disable, 1: Enable.
If the bypass is enabled, the PLL4 output is 24MHz.
29:25
/
/
/
24:20
/
/
/
19:16
/
/
/
15
/
/
/