Allwinner A20 - Page 43

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 43 / 812
Offset: 0x18
Register Name: PLL4_CFG_REG
Bit
Read/
Write
Default/Hex
Description
0: narrow, 1: wide.
14:13
/
/
/
12:8
R/W
0x19
PLL4_FACTOR_N.
PLL4 Factor N.
Factor=0, N=0;
Factor=1, N=1;
Factor=2, N=2;
……
Factor=31,N=31
7:6
/
/
/
5:4
R/W
0x1
PLL4_FACTOR_K.
PLL4 Factor K.(K=Factor + 1 )
The range is from 1 to 4.
3:2
/
/
/
1:0
R/W
0x1
/
1.5.4.7. PLL5-DDR(DEFAULT: 0X11049280)
Offset: 0x20
Register Name: PLL5_CFG_REG
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
PLL5_Enable.
0: Disable, 1: Enable.
The PLL5 output for DDR = (24MHz*N*K)/M.
The PLL5 output for other module =(24MHz*N*K)/P.
The PLL5 output is for the DDR.
Note: the output 24MHz*N*K clock must be in the range of
240MHz~2GHz if the bypass is disabled.
30
/
/
/
29
R/W
0x0
DDR_CLK_OUT_EN.
DDR clock output en.
28:25
/
/
/