Allwinner A20 - Page 44

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 44 / 812
Offset: 0x20
Register Name: PLL5_CFG_REG
Bit
Read/
Write
Default/Hex
Description
24:20
/
/
/
19
/
/
/
18
/
/
/
17:16
R/W
0x0
PLL5_OUT_EXT_DIV_P.
PLL5 Output External Divider P.
The range is 1/2/4//8.
15:13
/
/
/
12:8
R/W
0x12
PLL5_FACTOR_N.
PLL5 Factor N.
Factor=0, N=0;
Factor=1, N=1;
Factor=2, N=2
……
Factor=31,N=31
7
R/W
0x1
LDO_EN.
LDO Enable.
6
R/W
/
/
5:4
R/W
0x0
PLL5_FACTOR_K.
PLL5 Factor K.(K=Factor + 1 )
The range is from 1 to 4.
3:2
R/W
0x0
PLL5_FACTOR_M1.
PLL5 Factor M1.
1:0
R/W
0x0
PLL5_FACTOR_M.
PLL5 Factor M.(M = Factor + 1 )
The range is from 1 to 4.
1.5.4.8. PLL5-TUNING(DEFAULT: 0X14888000)
Offset: 0x24
Register Name: PLL5_TUN_REG
Bit
Read/
Write
Default/Hex
Description
31:29
/
/
/
28
/
/
/