Allwinner A20 - Page 45

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 45 / 812
Offset: 0x24
Register Name: PLL5_TUN_REG
Bit
Read/
Write
Default/Hex
Description
27
/
/
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26:24
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23
/
/
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22:16
/
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15
/
/
/.
14:8
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7
/
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6:0
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1.5.4.9. PLL6-SATA(DEFAULT: 0X21009911)
Offset: 0x28
Register Name: PLL6_CFG_REG
Bit
Read/
Write
Defaul
t/Hex
Description
31
R/W
0x0
PLL6_Enable.
0: Disable, 1: Enable.
There are two ouputs:
For SATA, the output =(24MHz*N*K)/M/6
If the SATA is on, the clock output should be equal to 100MHz;
For other module, the clock output = (24MHz*N*K)/2
PLL6*2 = 24MHz*N*K
Note: the output 24MHz*N*K clock must be in the range of
240MHz~2GHz if the bypass is disabled.
30
R/W
0x0
PLL6_BYPASS_EN.
PLL6 Output Bypass Enable.
0: Disable, 1: Enable.
If the bypass is enabled, the PLL6 output is 24MHz.
29:25
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24:20
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19:16
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