Allwinner A20 - Mixer Processor Block Diagram; MP Register List

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 311 / 812
3.1.2. Mixer Processor Block Diagram
DMA 0
DMA 1
DMA 2
DMA 3
Ch 0
Ch 1
Ch 2
Ch 3
CSC
0
CSC
1
Input
Fmt 0
Input
Fmt 1
Scaler
BLT /
ROP
Alpha /
CK
Data Channel Sorter
Rot
&
Mir0
Rot
&
Mir1
Rot
&
Mir2
Rot
&
Mir3
System DRAM
Controller
DMA
Controller
AHB BUS
Output
Fmt
CS
C 2
Input
Fmt 2
Input
Fmt 3
MP Register file
Command Queue Unit
3.1.3. MP Register List
Module name
Base address
MP
0x01e80000
Register name
Offset
Description
MP_CTL_REG
0x0
Mixer control register
MP_STS_REG
0x4
Mixer Status register
MP_IDMAGLBCTL_REG
0x8
Input DMA globe control register