Allwinner A20 - Page 312

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 312 / 812
Register name
Offset
Description
MP_IDMA_H4ADD_REG
0xC
Input DMA start address high 4bits register
MP_IDMA_L32ADD_REG
0x10 – 0x1C
Input DMA start address low 32bits register
MP_IDMALINEWIDTH_REG
0x20 – 0x2C
Input DMA line width register
MP_IDMASIZE_REG
0x30 – 0x3C
Input DMA memory block size register
MP_IDMACOOR_REG
0x40 – 0x4C
Input DMA memory block coordinate control
register
MP_IDMASET_REG
0x50 – 0x5C
Input DMA setting register
MP_IDMAFILLCOLOR_REG
0x60 – 0x6C
Input DMA fill-color register
MP_IDMASORT_REG
0x70
Input DMA channel sorter register
MP_CSC0CTL_REG
0x74
Color space converter 0 control register
MP_CSC1CTL_REG
0x78
Color space converter 1 control register
MP_SCACTL_REG
0x80
Scaler control register
MP_SCAOUTSIZE_REG
0x84
Scaling output size register
MP_SCAHORFCT_REG
0x88
Scaler horizontal scaling factor register
MP_SCAVERFCT_REG
0x8C
Scaler vertical scaling factor register
MP_SCAHORPHASE_REG
0x90
Scaler horizontal start phase setting register
MP_SCAVERPHASE_REG
0x94
Scaler vertical start phase setting register
MP_ROPCTL_REG
0xB0
ROP control register
MP_ROPIDX0CTL_REG
0xB8
ROP channel 3 index 0 control table setting
register
MP_ROPIDX1CTL_REG
0xBC
ROP channel 3 index 1 control table setting
register
MP_ALPHACKCTL_REG
0xC0
Alpha / Color key control register
MP_CKMIN_REG
0xC4
Color key min color register
MP_CKMAX_REG
0xC8
Color key max color register
MP_ROPOUTFILLCOLOR_RE
G
0xCC
Fill color of ROP output setting register
MP_CSC2CTL_REG
0xD0
Color space converter 2 control register
MP_OUTCTL_REG
0xE0
Output control register
MP_OUTSIZE_REG
0xE8
Output size register
MP_OUTH4ADD_REG
0xEC
Output address high 4bits register
MP_OUTL32ADD_REG
0xF0 – 0xF8
Output address low 32bits register
MP_OUTLINEWIDTH_REG
0x100 – 0x108
Output line width register