Allwinner A20 - MP Register Description

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 313 / 812
Register name
Offset
Description
MP_OUTALPHACTL_REG
0x120
Output alpha control register
MP_ICSCYGCOEF_REG
0x180 – 0x188
CSC0/1 Y/G coefficient register
MP_ICSCYGCONS_REG
0x18C
CSC0/1 Y/G constant register
MP_ICSCURCOEF_REG
0x190 – 0x198
CSC0/1 U/R coefficient register
MP_ICSCURCONS_REG
0x19C
CSC0/1 U/R constant register
MP_ICSCVBCOEF_REG
0x1A0 – 0x1A8
CSC0/1 V/B coefficient register
MP_ICSCVBCONS_REG
0x1AC
CSC0/1 V/B constant register
MP_OCSCYGCOEF_REG
0x1C0 – 0x1C8
CSC2 Y/G coefficient register
MP_OCSCYGCONS_REG
0x1CC
CSC2 Y/G constant register
MP_OCSCURCOEF_REG
0x1D0 – 0x1D8
CSC2 U/R coefficient register
MP_OCSCURCONS_REG
0x1DC
CSC2 U/R constant register
MP_OCSCVBCOEF_REG
0x1E0 – 0x1E8
CSC2 V/B coefficient register
MP_OCSCVBCONS_REG
0x1EC
CSC2 V/B constant register
Memory
0x200 – 0x27C
Scaling horizontal filtering coefficient RAM
block
0x280 – 0x2FC
Scaling vertical filtering coefficient RAM
block
0x400 – 0x7FF
Palette table
3.1.4. MP Register Description
3.1.4.1. MIXER CONTROL REGISTER
Offset: 0x0
Register Name: MP_CTL_REG
Bit
Read/W
rite
Default/He
x
Description
31:10
/
/
/
9
R/W
0
HWERRIRQ_EN
Hardware error IRQ enable control
0:disable