Allwinner A20 - Page 314

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 314 / 812
Offset: 0x0
Register Name: MP_CTL_REG
Bit
Read/W
rite
Default/He
x
Description
1:enable
8
R/W
0
FINISHIRQ_EN
Mission finish IRQ enable control
0:disable
1:enable
7:2
/
/
/
1
R/W
0
START_CTL
Start control
If the bit is set, the module will start 1 frame operation and stop
auto.
0
R/W
0
MP_EN
Enable control
0:disable
1:enable
3.1.4.2. MIXER STATUS REGISTER
Offset: 0x4
Register Name: MP_STS_REG
Bit
Read/W
rite
Default/H
ex
Description
31:14
/
/
/
13
R
0
HWERR_FLAG
Hardware error status
12
R
0
BUSY_FLAG
Module working status
0:idle
1:running
11:10
/
/
/
9
R/W
0
HWERRIRQ_FLAG
Hardware error IRQ
It will be set when hardware error occur, and cleared by writing
1.
8
R/W
0
FINISHIRQ_FLAG