Allwinner A20 - Page 315

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 315 / 812
Offset: 0x4
Register Name: MP_STS_REG
Bit
Read/W
rite
Default/H
ex
Description
Mission finish IRQ
It will be set when 1 frame operation accomplished, and cleared
by writing 1.
7:0
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3.1.4.3. INPUT DMA GLOBE CONTROL REGISTER
Offset: 0x8
Register Name: MP_IDMAGLBCTL_REG
Bit
Read/W
rite
Default/H
ex
Description
31:10
/
/
/
9:8
R/W
0
MEMSCANORDER
Memory scan order selection
0:
Top to down
Left to right
1:
Top to down
Right to left
2:
Down to top
Left to right
3:
Down to top
Right to left
Note:
----Four input DMA channel use the same scan rule.
----The each output DMA channel should match the same
memory scan order rule with the input DMA channel.
7:0
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