Allwinner A20 - Page 316

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 316 / 812
3.1.4.4. INPUT DMA START ADDRESS HIGH 4BITS REGISTER
Offset: 0xC
Register Name: MP_IDMA_H4ADD_REG
Bit
Read/W
rite
Default/H
ex
Description
31:28
/
/
/
27:24
R/W
0
IDMA3_H4ADD
iDMA3
High 4bits address in bits
23:20
/
/
/
19:16
R/W
0
IDMA2_H4ADD
iDMA2
High 4bits address in bits
15:12
/
/
/
11:8
R/W
0
IDMA1_H4ADD
iDMA1
High 4bits address in bits
7:4
/
/
/
3:0
R/W
0
IDMA0_H4ADD
iDMA0
High 4bits address in bits
3.1.4.5. INPUT DMA START ADDRESS LOW 32BITS REGISTER
Offset:
iDMA0:0x10
iDMA1:0x14
iDMA2:0x18
iDMA3:0x1C
Register Name: MP_IDMA_L32ADD_REG
Bit
Read/W
rite
Default/
Hex
Description
31:0
R/W
0
IDMA_L32ADD
iDMA
Low 32bits address in bits