Allwinner A20 - System Control Register List; System Control Register

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 98 / 812
1.7.2. System Control Register List
Module Name
Base Address
SYS_CTRL
0x01C00000
Register Name
Offset
Description
SRAM_CTRL_REG0
0x0
SRAM Control Register 0
SRAM_CTRL_REG1
0x4
SRAM Control Register 1
VER_REG
0x24
Version Register
NMI_IRQ_CTRL_REG
0x30
NMI Interrupt Control Register
NMI_IRQ_PEND_REG
0x34
NMI Interrupt Pending Register
NMI_IRQ_ENABLE_REG
0x38
NMI Interrupt Enable Register
1.7.3. System Control Register
1.7.3.1. SRAM CONTROL REGISTER 0(DEFAULT: 0X7FFFFFFF)
Offset: 0x0
Register Name: SRAM_CTRL_REG0
Bit
Read/
Write
Default/Hex
Description
31
/
/
/
30:0
R/W
0x7fffffff
SRAM_C1_MAP.
SRAM Area C1 50K Bytes Configuration by AHB.
0: map to CPU/DMA
1: map to VE
1.7.3.2. SRAM CONTROL REGISTER 1(DEFAULT: 0X00001300)
Offset: 0x4
Register Name: SRAM_CTRL_REG1
Bit
Read/
Write
Default/Hex
Description