Allwinner A20 - Page 99

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 99 / 812
Offset: 0x4
Register Name: SRAM_CTRL_REG1
Bit
Read/
Write
Default/Hex
Description
31
R/W
0x0
BIST_NDMA_CTRL_SEL.
Bist and Normal DMA control select.
0: N-DMA, 1: Bist.
30:13
/
/
/.
12
R/W
0x1
SRAM_C3_MAP.
SRAM C3 map config.
0: map to CPU/BIST
1: map to ISP
11:10
/
/
/
9:8
R/W
0x3
SRAM_C2_MAP.
SRAM C2 map config.
0: map to CPU/BIST
1: map to AE
2: map to CE
3: map to ACE
7:6
/
/
/.
5:4
R/W
0x0
SRAM_A3_A4_MAP.
SRAM Area A3/A4 Configuration by AHB.
00: map to CPU/DMA
01: map to EMAC
10: /
11: /
3:1
/
/
/.
0
R/W
0x0
SRAMD_MAP.
SRAM D Area Config.
0: map to CPU/DMA
1: map to USB0
1.7.3.3. VERSION REGISTER(DEFAULT: 0X00000000)
Offset: 0x24
Register Name: VER_REG
Bit
Read/
Write
Default/He
x
Description