Allwinner A20 - Page 138

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 138 / 812
Offset:0x10
Register Name: HS_TMR0_CTRL_REG
Bit
Read/
Write
Default/He
x
Description
101: /
110: /
111: /
3:2
/
/
/
1
R/W
0x0
HS_TMR0_RELOAD.
High Speed Timer 0 Reload.
0: No effect, 1: Reload High Speed Timer 0 Interval Value.
0
R/W
0x0
HS_TMR0_EN.
High Speed Timer 0 Enable.
0: Stop/Pause, 1: Start.
If the timer is started, it will reload the interval value to internal
register, and the current counter will count from interval value
to 0.
If the current counter does not reach the zero, the timer enable
bit is set to “0”, the current value counter will pause. At least
wait for 2 cycles, the start bit can be set to 1.
In timer pause state, the interval value register can be
modified. If the timer is started again, and the Software hope
the current value register to down-count from the new interval
value, the reload bit and the enable bit should be set to 1 at the
same time.
1.10.3.4. HS TIMER 0 INTERVAL VALUE LO REGISTER
Offset:0x14
Register Name: HS_TMR0_INTV_LO_REG
Bit
Read/
Write
Default/H
ex
Description
31:0
R/W
x
HS_TMR0_INTV_VALUE_LO.
High Speed Timer 0 Interval Value [31:0].
1.10.3.5. HS TIMER 0 INTERVAL VALUE HI REGISTER
Offset:0x18
Register Name: HS_TMR0_INTV_HI_REG
Bit
Read/
Write
Default/He
x
Description
31:24
/
/
/