Allwinner A20 - Page 112

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 112 / 812
Offset: 0x4
Register Name: TMR_IRQ_STA_REG
Bit
Read/
Write
Default/Hex
Description
1
R/W
0x0
TMR1_IRQ_PEND.
Timer 1 IRQ Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending, timer 1 interval value is reached.
0
R/W
0x0
TMR0_IRQ_PEND.
Timer 0 IRQ Pending. Set 1 to the bit will clear it.
0: No effect, 1: Pending, timer 0 interval value is reached.
1.9.3.3. TIMER 0 CONTROL REGISTER(DEFAULT: 0X00000004)
Offset: 0x10
Register Name: TMR0_CTRL_REG
Bit
Read/
Write
Default/Hex
Description
31:8
/
/
/.
7
R/W
0x0
TMR0_MODE.
Timer 0 mode.
0: Continuous mode. When interval value reached, the timer will
not disable automatically.
1: Single mode. When interval value reached, the timer will
disable automatically.
6:4
R/W
0x0
TMR0_CLK_PRES.
Select the pre-scale of timer 0 clock source.
000: /1
001: /2
010: /4
011: /8
100: /16
101: /32
110: /64
111: /128
3:2
R/W
0x1
TMR0_CLK_SRC.
Timer 0 Clock Source.
00: Low speed OSC,
01: OSC24M.
10: PLL6/6