Allwinner A20 - Page 113

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 113 / 812
Offset: 0x10
Register Name: TMR0_CTRL_REG
Bit
Read/
Write
Default/Hex
Description
11: /.
1
R/W
0x0
TMR0_RELOAD.
Timer 0 Reload.
0: No effect, 1: Reload timer 0 Interval value.
0
R/W
0x0
TMR0_EN.
Timer 0 Enable.
0: Stop/Pause, 1: Start.
If the timer is started, it will reload the interval value to internal
register, and the current counter will count from interval value to
0.
If the current counter does not reach the zero, the timer enable
bit is set to “0”, the current value counter will pause. At least
wait for 2 Tcylces, the start bit can be set to 1.
In timer pause state, the interval value register can be modified.
If the timer is started again, and the Software hope the current
value register to down-count from the new interval value, the
reload bit and the enable bit should be set to 1 at the same time.
Note: the time between the timer disabled and enabled should be larger than 2*Tcycles(Tcycles=
Timer clock source/pre-scale).
1.9.3.4. TIMER 0 INTERVAL VALUE REGISTER
Offset: 0x14
Register Name: TMR0_INTV_VALUE_REG
Bit
Read/
Write
Default/Hex
Description
31:0
R/W
x
TMR0_INTV_VALUE.
Timer 0 Interval Value.
Note: when you set the value, please take into consideration the system clock and the timer clock
source.
1.9.3.5. TIMER 0 CURRENT VALUE REGISTER
Offset: 0x18
Register Name: TMR0_CUR_VALUE_REG
Bit
Read/
Write
Default/Hex
Description