Allwinner A20 - Page 36

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 36 / 812
Register Name
Offset
Description
PLL3_CFG_REG
0x0010
PLL3 CONTROL
PLL4_CFG_REG
0x0018
PLL4 CONTROL
PLL5_CFG_REG
0x0020
PLL5 CONTROL
PLL5_TUN_REG
0x0024
PLL5 TUNING
PLL6_CFG_REG
0x0028
PLL6 CONTROL
PLL6_TUN_REG
0x002C
PLL6 TUNING
PLL7_CFG_REG
0x0030
PLL7 CONTROL
/
0x0034
/
PLL1_TUN2_REG
0x0038
PLL1 TUNING2
PLL5_TUN2_REG
0x003C
PLL5 TUNING2
PLL8_CFG_REG
0x0040
PLL8 CONTROL
OSC24M_CFG_REG
0x0050
OSC24M CONTROL
CPU_AHB_APB0_CFG_REG
0x0054
CPU, AHB AND APB0 DIVIDE RATIO
APB1_CLK_DIV_REG
0x0058
APB1 CLOCK DIVIDOR
AHB_GATING_REG0
0x0060
AHB MODULE CLOCK GATING 0
AHB_GATING_REG1
0x0064
AHB MODULE CLOCK GATING 1
APB0_GATING_REG
0x0068
APB0 MODULE CLOCK GATING
APB1_GATING_REG
0x006C
APB1 MODULE CLOCK GATING
NAND_SCLK_CFG_REG
0x0080
NAND CLOCK CONFIGURATION
REGISTER
MS_SCLK_CFG_REG
0x0084
MEMORY STICK CLOCK
CONFIGURATION REGISTER
SD0_CLK_REG
0x0088
SD0 CLOCK REGISTER
SD1_CLK_REG
0x008C
SD1 CLOCK REGISTER
SD2_CLK_REG
0x0090
SD2 CLOCK REGISTER
SD3_CLK_REG
0x0094
SD3 CLOCK REGISTER
TS_CLK_REG
0x0098
TRANSPORT STREAM CLOCK
REGISTER
SS_CLK_REG
0x009C
SECURITY SYSTEM CLOCK REGISTER
SPI0_CLK_REG
0x00A0
SPI0 CLOCK REGISTER
SPI1_CLK_REG
0x00A4
SPI1 CLOCK REGISTER
SPI2_CLK_REG
0x00A8
SPI2 CLOCK REGISTER
IR0_CLK_REG
0x00B0
IR0 CLOCK REGISTER