A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 588 / 812
register for current status. A transfer has to be concluded with STOP condition by setting M_STP bit
high.
In Slave Mode, the TWI also constantly samples the bus and look for its own slave address during
addressing cycles. Once a match is found, it is addressed and interrupt the CPU host with the
corresponding status. Upon request, the CPU host should read the status, read/write 2WIRE_DATA
data register, and set the 2WIRE_CNTR control register. After each byte transfer, a slave device
always halt the operation of remote master by holding the next low pulse on SCL line until the
microprocessor responds to the status of previous byte transfer or START condition.
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