Allwinner A20 - Page 26

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 26 / 812
1.4.3.3. CPU0 STATUS REGISTER(DEFAULT : 0X00000000)
Offset: 0x48
Register Name: CPU0_ STATUS
Bit
Read/
Write
Default/Hex
Description
31:3
/
/
/.
2
R
0x0
STANDBYWFI.
Indicates if the processor is in WFI standby mode:
0: Processor not in WFI standby mode.
1: Processor in WFI standby mode
1
R
0x0
STANDBYWFE.
Indicates if the processor is in the WFE standby mode:
0: Processor not in WFE standby mode
1: Processor in WFE standby mode
0
R
0x0
SMP_AMP
0: AMP mode
1: SMP mode
1.4.3.4. CPU1 RESET CONTROL(DEFAULT: 0X00000000)
Offset: 0x80
Register Name: CPU1_RST_CTRL
Bit
Read/
Write
Default/Hex
Description
31:2
/
/
/.
1
R/W
0x0
CPU1_CORE_REST.
These are the primary reset signals which initialize the
processor logic in the processor power domains, not including
the debug, breakpoint and watchpoint logic.
0: assert
1: de-assert.
0
R/W
0x0
CPU1_RESET.
CPU1 Reset Assert.
These power-on reset signals initialize all the processor logic,
including CPU Debug, and breakpoint and watch point logic in
the processor power domains. They do not reset debug logic
in the debug power domain.
0: assert
1: de-assert.