Allwinner A20 - Page 175

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 175 / 812
Offset: 0x4
Register Name: AC_DAC_FIFOC
Bit
Read/Write
Default
Description
25:24
R/W
0x0
FIFO_MODE.
For 24-bits transmitted audio sample:
00/10: FIFO_I[23:0] = {TXDATA[31:8]}
01/11: Reserved
For 16-bits transmitted audio sample:
00/10: FIFO_I[23:0] = {TXDATA[31:16], 8’b0}
01/11: FIFO_I[23:0] = {TXDATA[15:0], 8’b0}
23
/
/
/
22:21
R/W
0x0
DAC_DRQ_CLR_CNT.
When TX FIFO available room less than or equal N, DRQ
Request will be de-asserted. N is defined here:
00: IRQ/DRQ Deasserted when WLEVEL > TXTL
01: 4
10: 8
11: 16
20:15
/
/
/
14:8
R/W
0x10
TX_TRIG_LEVEL.
TX FIFO Empty Trigger Level (TXTL[12:0])
Interrupt and DMA request trigger level for TX FIFO normal
condition.
IRQ/DRQ Generated when WLEVEL
≤
TXTL
Notes:
WLEVEL represents the number of valid samples in the TX
FIFO
7
R/W
0x0
ADDA_LOOP_EN.
ADDA loop Enable, adda
0: Disable 1: Enable
6
R/W
0x0
DAC_MONO_EN.
DAC Mono Enable
0: Stereo, 64 levels FIFO
1: mono, 128 levels FIFO
When enabled, L & R channel send same data
5
R/W
0x0
TX_SAMPLE_BITS.
Transmitting Audio Sample Resolution
0: 16 bits
1: 24 bits