Allwinner A20 - Page 176

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 176 / 812
Offset: 0x4
Register Name: AC_DAC_FIFOC
Bit
Read/Write
Default
Description
4
R/W
0x0
DAC_DRQ_EN.
DAC FIFO Empty DRQ Enable
0: Disable
1: Enable
3
R/W
0x0
DAC_IRQ_EN.
DAC FIFO Empty IRQ Enable
0: Disable
1: Enable
2
R/W
0x0
FIFO_UNDERRUN_IRQ_EN.
DAC FIFO Under Run IRQ Enable
0: Disable
1: Enable
1
R/W
0x0
FIFO_OVERRUN_IRQ_EN.
DAC FIFO Over Run IRQ Enable
0: Disable
1: Enable
0
R/W
0x0
FIFO_FLUSH.
DAC FIFO Flush
Write ‘1’ to flush TX FIFO, self clear to ‘0’
1.13.4.3. DAC FIFO STATUS REGISTER
Offset: 0x8
Register Name: AC_DAC_FIFOS
Bit
Read/Write
Default
Description
31:24
/
/
/
23
R
0x1
TX_EMPTY.
TX FIFO Empty
0: No room for new sample in TX FIFO
1: More than one room for new sample in TX FIFO (>= 1 word)
22:8
R
0x80
TXE_CNT.
TX FIFO Empty Space Word Counter
7:4
/
/
/
3
R/W
0x1
TXE_INT.
TX FIFO Empty Pending Interrupt