Allwinner A20 - Page 177

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 177 / 812
Offset: 0x8
Register Name: AC_DAC_FIFOS
Bit
Read/Write
Default
Description
0: No Pending IRQ
1: FIFO Empty Pending Interrupt
Write ‘1’ to clear this interrupt or automatic clear if interrupt
condition fails.
2
R/W
0x0
TXU_INT.
TX FIFO Under run Pending Interrupt
0: No Pending Interrupt
1: FIFO Under run Pending Interrupt
Write ‘1’ to clear this interrupt
1
R/W
0x0
TXO_INT.
TX FIFO Overrun Pending Interrupt
0: No Pending Interrupt
1: FIFO Overrun Pending Interrupt
Write ‘1’ to clear this interrupt
0
/
/
/
1.13.4.4. DAC TX DATA REGISTER
Offset: 0xC
Register Name: AC_DAC_TXDATA
Bit
Read/Write
Default
Description
31:0
W
0x0
TX_DATA.
Transmitting left, right channel sample data should be written
this register one by one. The left channel sample data is first
and then the right channel sample.
1.13.4.5. DAC ANALOG CONTROL REGISTER
Offset:0x10
Register Name: AC_DAC_ACTRL
Bit
R/W
Default
Description
31
R/W
0x0
DACAREN.
Internal DAC Analog Right channel Enable
0:Disable
1:Enable
30
R/W
0x0
DACALEN.