6100B/6105A
Users Manual
5-14
5-31. Instrument Model Structure
The IEEE 488.2 Standard provides for an extensive hierarchical structure with the Status
Byte at the apex, defining its bits 4, 5 and 6 and their use as summaries of a Standard–
defined event structure, which must be included if the device is to claim conformance with
the Standard. The instrument employs these bits as defined in the Standard.
Bits 0, 1, 2 and 3 and 7 are available to the device designer; only bits 3 and 7 are used in the
instrument, and these are as defined by the SCPI standard. The application programmer
must recognize that whenever the application program reads the Status Byte, it can only
receive summaries of types of events, and further query messages will be needed to probe
the details relating to the events themselves. For example: a further byte is used to expand
on the summary at bit 5 of the Status Byte.
5-32. Status Byte Register
In this structure the Status Byte is held in the Status Byte Register; the bits being allocated
as follows:
• Bits: 0 (DIO1), 1 (DIO2) and 2 (DIO3) are not used in the instrument status byte. They
are always false.
• Bit 3 summarizes the state of the Questionable Status data, held in the Questionable
Status register (QSR), whose bits represent SCPI-defined and device-dependent
conditions in the instrument. The QSS bit is true when the data in the QSR contains one
or more enabled bits, which are true, or false, when all the enabled bits in the byte are
false. The SCPI Standard defines the QSR and its data, (not used in 6100B).
• Bit 4 (DIO5) IEEE 488.2 defined Message Available Bit (MAV).
The MAV bit helps to synchronize information exchange with the controller. It is true
when a message is placed in the Output Queue; or false when the Output Queue is
empty. The common command *CLS can clear the Output Queue and the MAV bit 4 of
the Status Byte Register; providing it is sent immediately following a Program Message
Terminator.
• Bit 5 (DIO6) IEEE 488.2 defined Standard Event Summary Bit (ESB).
Summarizes the state of the Event Status byte, held in the Event Status Register (ESR),
whose bits represent IEEE 488.2-defined conditions in the device. The ESB bit is true
when the byte in the ESR contains one or more enabled bits which are true; or false
when all the enabled bits in the byte are false.
• Bit 6 (DIO7) is the Master Status Summary Message (MSS bit), and is set true if one of
the bits 0 to 5 or bit 7 is true (bits 0, 1 and 2 are always false in the instrument).
• Bit 7 (DIO4) SCPI defined Operation Status Summary Bit (QSS).
Summarizes the state of the Operation Status data, held in the Operation Status register
(OSR), whose bits represent processes in progress in the instrument. The OSS bit is true
when the data in the OSR contains one or more enabled bits which are true, or false
when all the enabled bits in the byte are false. The OSR is not used in the 6100B.
5-33. Reading the Status Byte Register
The common query:*STB? reads the binary number in the Status Byte register. The
response is in the form of a decimal number that is the sum of the binary weighted values in
the enabled bits of the register. In the instrument, the binary weighted values of bits 0, 1 and
2 are always zero.
5-34. Service Request Enable Register
The SRE register is a means for the application program to select, by enabling individual
Status Byte summary bits, those types of events which are to cause the instrument to
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