6100B/6105A
Users Manual
5-16
Note about the ERROR Queue
The Error Queue is a sequential memory stack. Each reportable error has been
given a listed number and explanatory message, which are entered into the error
queue as the error occurs. The queue is read destructively as a First In/ First Out
stack, using the query command SYSTem:ERRor? to obtain a code number and
message.
Repeated use of the query SYSTem:ERRor? will read successive Device Dependent,
Command and Execution errors until the queue is empty, when the “Empty”
message (0,"No error") will be returned.
It would be good practice to repeatedly read the Error Queue until the “Empty”
message is returned. The common command *CLS clears the queue.
• Bit 4 Execution Error (EXE).
An execution error is generated if the received command cannot be executed, owing to
the device state or the command parameter being out of bounds. The appropriate error
message is added to the ERROR Queue.
See the “Note about the Error Queue” above.
• Bit 5 Command Error (CME).
CME occurs when a received bus command does not satisfy the IEEE 488.2 generic
syntax or the device command syntax programmed into the instrument interface’s parser,
and so is not recognized as a valid command. The appropriate error message is added to
the Error Queue. See the “Note about the ERROR Queue” above.
• Bit 6 User Request (URQ).
This bit is not used. It is always set false.
• Bit 7 Instrument Power Supply On (PON).
This bit is set true only when the Line Power has just been switched on to the
instrument.
Whether or not an SRQ is generated by setting bit 7 true, depends on the previously-
programmed Power On Status Clear message *PSC phs Nrf:
• For an Nrf of 1, the Event Status Enable register would have been cleared at power
on, so PON would not generate the ESB bit in the Status Byte register, and no SRQ
would occur at power on.
• If Nrf was 0, and the Event Status Enabling register bit 7 true, and the Service
Request Enabling register bit 5 true; a change from Power Off to Power On will
generate an SRQ. This is only possible because the enabling register conditions are
held in non volatile memory, and restored at power on. This facility is included to
allow the application program to set up conditions so that a momentary Power Off
followed by reversion to Power On (which could upset the instrument programming)
will be reported by SRQ.
To achieve this, the Event Status register bit 7 must be permanently true (by *ESE phs
Nrf , where Nrf ≥128); the Status Byte Enable register bit 5 must be set permanently
true (by command *SRE phs Nrf , where Nrf lies in one of the ranges 32 - 63, 96 - 127,
160 - 191, or 224 - 255); Power On Status Clear must be disabled (by *PSC phs Nrf,
where Nrf = 0); and the Event Status register must be read destructively immediately
following the Power On SRQ (by the common query *ESR?).
5-37. Standard Event Status Enable Register
The ESE register is a means for the application program to select, from the positions of the
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