Parameter Address
Default Min Max Unit Logic Diagram
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MAIN: IP,max prim.stored b
006 161
Not measured 0 65000 A
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Display of the delayed stored maximum phase current of end b as a primary
quantity.
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MAIN: Curr. IP,max,c prim.
005 103
Not measured 0 65000 A
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Display of the maximum phase current as a primary quantity, end c.
[spacer]
MAIN: IP,max prim.,delay c
007 162
Not measured 0 65000 A
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Display of the delayed maximum current of end c as a primary quantity.
[spacer]
MAIN: IP,max prim.stored c
007 161
Not measured 0 65000 A
[spacer]
Display of the delayed stored maximum phase current of end c as a primary
quantity.
[spacer]
MAIN: Curr. IP,max,d prim.
005 115
Not measured 0 65000 A
[spacer]
Display of the maximum phase current of end a, b, c or d, respectively, as a
primary quantity.
[spacer]
MAIN: IP,max prim.,delay d
008 162
Not measured 0 65000 A
[spacer]
Display of the delayed maximum current of end a, b, c or d, respectively, as a
primary quantity.
[spacer]
MAIN: IP,max prim.stored d
008 161
Not measured 0 65000 A
[spacer]
Display of the delayed stored maximum phase current of end a, b, c or d,
respectively, as a primary quantity.
[spacer]
MAIN: Curr. IP,min,a prim.
005 104
Not measured 0 65000 A Fig. 3-46, (p. 3-78)
[spacer]
Display of the minimum phase current of end a as a primary quantity.
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MAIN: Curr. IP,min,b prim.
005 105
Not measured 0 65000 A
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Display of the minimum phase current of end b as a primary quantity.
[spacer]
MAIN: Curr. IP,min,c prim.
005 106
Not measured 0 65000 A
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Display of the minimum phase current of end c as a primary quantity.
8 Information and Control Functions P634
P634/EN M/R-42-A // P634‑311‑653 8-5