LCD Controller
MOTOROLA MPC823e REFERENCE MANUAL 18-19
LCD CONTROLLER
18
18.3.9.4 ANALOG INTERFACE. The MPC823e has a digital interface, so you will need a
DAC to connect the MPC823e to an analog panel.
18.3.10 System Considerations
When you are designing a system with the LCD controller, you must monitor the bus
bandwidth used by the LCD subsystem and the maximum allowable bus latency. The
configuration below uses the following parameters:
• GCLK2/CLKOUT—System clock frequency
• BNUM—Number of bursts per frame
• FRR—Frame refresh rate
• BPIX—Number of bits per pixel
• COL—Number of display columns
• ROW—Number of display rows
• MB—Number of system clocks per memory burst
You must configure the parallel to serial clock ratio between the system clock and the LCD
serial data clock. The following example contains typical display characteristics for a full
VGA panel (640 × 480) calculation:
• 640 × 480 = 307,200 pixels per screen
• (307,200 pixels per screen) × 4 bits per pixel = 1.228Mb per screen = 150Kb per screen
• 70Hz × 150Kb = 10.5Mb/s
• 70Hz is 14.3ms per frame: 14.3ms/307,200 pixels clocked 4 bits at a time = 186ns
(approximately 5MHz) serial clock to the LCD drivers
The display serial clock is slightly faster than 5MHz because of the panel overhead. In most
VGA displays, however, an 8-bit LCD serial data (dual-scan passive panel) is used and the
display frequency is 3.76MHz. The CLKOUT to LCDCLK ratio must be between 4:1 and 5:1
for optimum system operation.
18.3.10.1 BUS BANDWIDTH. The bus bandwidth that the LCD controller uses depends on
the display parameters (size, refresh rate), the memory system (number of clocks per burst),
and the system clock frequency.
BNUM
COL ROW BPIX××
128
-------------------------------------------------------=
Bus Band Width
BNUM FRR MB××
SCLK
-----------------------------------------------------
100%×=
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