Video Controller
MOTOROLA MPC823e REFERENCE MANUAL 19-15
VIDEO CONTROLLER
19
19.3.10 Video Frame Buffer B Start Address Register (Set 1)
The 32-bit video frame buffer B start address register set 1 (VFBA1) holds the start address
of the set_1 even field. Since all bursts are required to be 16-byte aligned, this register does
not use the four least-significant bits of the address.
FBA1—Frame Buffer B Start Address for Set 1
This field designates the start address of the frame buffer B set 0 in system memory.
VFBA1
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD FBA1
RESET —
R/W R/W
ADDR (IMMR & 0xFFFF0000) + 0x824
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD FBA1 X
RESET ——
R/W R/W R/W
ADDR (IMMR & 0xFFFF0000) + 0x826
NOTE: X = “Don’t Care” and — = Undefined.
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