Video Controller
MOTOROLA MPC823e REFERENCE MANUAL 19-17
VIDEO CONTROLLER
19
19.4.1 Video RAM Word Format
The video RAM word specifies the timing of all external signals controlled by the video
controller.
HR—Horizontal Sync on Rising Edge of the Clock
0 = The value of the HSYNC
signal will be 0 after the rising edge of the clock.
1 = The value of the HSYNC
signal will be 1 after the rising edge of the clock.
HF—Horizontal Sync on Falling Edge of the Clock
0 = The value of the HSYNC
signal will be 0 after the falling edge of the clock.
1 = The value of the HSYNC
signal will be 1 after the falling edge of the clock.
VR—Vertical Sync on Rising Edge of the Clock
0 = The value of the VSYNC
signal will be 0 after the rising edge of the clock.
1 = The value of the VSYNC
signal will be 1 after the rising edge of the clock.
VF—Vertical Sync on Falling Edge of the Clock
0 = The value of the VSYNC
signal will be 0 after the falling edge of the clock.
1 = The value of the VSYNC
signal will be 1 after the falling edge of the clock.
FR—Field on Rising Edge of the Clock
0 = The value of the FIELD signal will be 0 after the rising edge of the clock.
1 = The value of the FIELD signal will be 1 after the rising edge of the clock.
FF—Field on Falling Edge of the Clock
0 = The value of the FIELD signal will be 0 after the falling edge of the clock.
1 = The value of the FIELD signal will be 1 after the falling edge of the clock.
VIDEO RAM WORD
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD HR HF VR VF FR FF BR BF RESERVED VDS
RESET ———————— — —
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR (IMMR & 0xFFFF0000) + 0xB00–0xBFE
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD INT RESERVED LCYC/CNT LP LST
RESET —— — ——
R/W R/W R/W R/W R/W R/W
ADDR (IMMR & 0xFFFF0000) + 0xB00–0xBFF
NOTE: — = Undefined.
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