Motorola MPC823e - Page 386

Memory Controller
15-28 MPC823e REFERENCE MANUAL MOTOROLA
MEMORY CONTROLLER
15
Anywhere from 0 to 30 wait states can be programmed for TA generation. The WEx signals
are available for each byte that is written to memory. Also, an OE
signal is provided to
eliminate external glue logic. On system reset, a global chip-select (CS0
) is asserted to
provide a boot ROM chip-select before the system is fully configured.
Table 15-2. GPCM Strobe Signal Behavior
OPTION REGISTER
ATTRIBUTES
SIGNAL BEHAVIOR
TRLX ACCESS
TYPE
EBDF CSNT ACS
ADDRESS
TO CS
x
ASSERTED
ADDRESS
TO OE
ASSERTED
ADDRESS
TO WEx
ASSERTED
DATA
TO WEx
ASSERTED
CS
x
NEGATED
TO
ADD/DATA
INVALID
WE
x
NEGATED
TO
ADD/DATA
INVALID
TOTAL
NUMBER
OF
CYCLES
0
Read
—
—
00 0
3/4*Clock
——
1/4* Clock
—
2+SCY
10 1/4*Clock
11 1/2*Clock
Write
0
00 0
—
1/4*Clock
10 1/4*Clock
3/4*Clock -1/4*Clock
11 1/2*Clock
00
1
00 0
1/2*Clock
10 1/4*Clock
1/2*Clock
11 1/2*Clock
01
00 0 1/4*Clock
3/8*Clock
10 1/4*Clock
3/8*Clock
11 1/2*Clock
1
Read
—
—
00 0 3/4*Clock
——
1/4*Clock
—
2+2*SCY
10 (1+1/4)*Clock 1+3/4*Clock
3+2*SCY
11 (1+1/2)*Clock 1+3/4*Clock
Write
0
00 0
—
3/4*Clock -1/4*Clock
1/4*Clock
2+2*SCY
10 (1+1/4)*Clock 1+3/4*Clock 3/4*Clock
3+2*SCY
11 (1+1/2)*Clock 1+3/4*Clock 3/4*Clock
00
1
00 0 3/4*Clock -1/4*Clock
1+1/2*Clock
10 (1+1/4)*Clock 1+3/4*Clock 3/4*Clock
1+1/2*Clock 4+2*SCY
11 (1+1/2)*Clock 1+3/4*Clock 3/4*Clock
01
00 0 3/4*Clock -1/4*Clock 1/4*Clock
1+3/8*Clock
3+2*SCY
10 (1+1/4)*Clock 1+3/4*Clock 3/4*Clock
1+3/8*Clock 4+2*SCY
11 (1+1/2)*Clock 1+3/4*Clock 3/4*Clock
NOTE: SCY is the number of wait cycles from the option register.