Motorola MPC823e - Page 396

Memory Controller
15-38 MPC823e REFERENCE MANUAL MOTOROLA
MEMORY CONTROLLER
15
15.4.1.4 SRAM INTERFACE. Figure 15-17 illustrates a simple connection between an
SRAM device and the MPC823e.
15.4.1.5 EXTERNAL ASYNCHRONOUS MASTER SUPPORT. Figure 15-18 illustrates
the basic interface between an asynchronous external master and the GPCM to allow
connection to “static RAM” memory.
MEMORY 32-BIT WIDE SRAM
Figure 15-17. GPCM to SRAM Configuration
Figure 15-18. Asynchronous External Master Configuration For
GPCM-Handled Memory Devices
WEx
CE
OE
ADDRESS
DATA
WE
x
CSx
GPL_x1 / OE
A[15:29]
D[0:31]
128K
ADDRESS
CE
OE
W
DATA
ADDRESS
CS
x
OE
WEx
DATA
ASYNCHRONOUS EXTERNAL MASTER
ASTA
TA
AS
ADDRESS
DATA
MEMORY
MPC823e