Memory Controller
MOTOROLA MPC823e REFERENCE MANUAL 15-39
MEMORY CONTROLLER
15
Figure 15-19 illustrates the timing for TRLX = 0 when an external asynchronous master
accesses SRAM. The TA
signal remains asserted with the WEx and OE signals until the AS
signal is negated by the external master.
When an external asynchronous master performs an access to a memory device via the
general-purpose chip-select machine in the memory controller, the CSNT bit in the option
register is configured as “don’t care”.
Figure 15-19. Asynchronous External Master, GPCM-Handled
Memory Access Timing (TRLX = 0)
CLOCK
ADDRESS
CS
WE
OE
DATA
TA
AS
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