Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-237
COMMUNICATION
16
SCCs
• C_MASK—For the 16-bit CRC-CCITT, C_MASK must be initialized with 0x0000F0B8.
For the 32-bit CRC-CCITT, C_MASK must be initialized with 0xDEBB20E3.
• C_PRES—For the 16-bit CRC-CCITT, C_PRES must be initialized with 0x0000FFFF.
For the 32-bit CRC-CCITT, C_PRES must be initialized with 0xFFFFFFFF.
• DISFC, CRCEC, ABTSC, NMARC, and RETRC—These 16-bit (modulo 2
16
) counters
are maintained by the communication processor module. You can initialize the following
counters while the channel is disabled.
❏ DISFC–Discarded Frame Counter (error-free frames, but no free buffers).
❏ CRCEC–CRC Error Counter. Includes frames not addressed to you or frames
received in the BSY condition, but does not include overrun errors.
❏ ABTSC–Abort Sequence Counter.
❏ NMARC–Nonmatching Address Received Counter (error-free frames only).
❏ RETRC–Frame Retransmission Counter (due to collision).
• MFLR—The SCCx HDLC controller compares the length of an incoming HDLC frame
with the user-defined value given in this 16-bit register. If this limit is exceeded, the
remainder of the incoming HDLC frame is discarded and the LG bit is set in the last RX
buffer descriptor belonging to that frame. The SCCx HDLC controller waits until the end
of the frame and then reports the frame status and length in the last RX buffer
descriptor. The MFLR is defined as all the in-frame bytes between the opening and
closing flags.
• MAX_CNT—A temporary down-counter used to track the frame length.
• RFTHR—The received frame’s threshold value is used to reduce the interrupt overhead
that might otherwise occur when a series of short HDLC frames arrives, each causing
an RXF interrupt. By setting the RFTHR value, you limit the frequency of RXF interrupts,
which only occurs when the RFTHR value is reached.
• RFCNT—A temporary down-counter used to implement the RFTHR feature.
• HMASK, HADDR1, HADDR2, HADDR3, and HADDR4—The SCCx HDLC controller
has five 16-bit registers for address recognition: one mask register and four address
registers. The SCCx HDLC controller reads the frame address from the HDLC receiver,
compares it against the four address register values, and then masks the result with the
user-defined mask register. A one in the mask register represents a bit position for
which address comparison must occur and a zero represents a masked bit position.
When an address match is made, the address and the data following it are written into
the data buffers. When the addresses are not matched and the frame is error-free, the
nonmatching address received counter (NMARC) is incremented.
Note: You must provide enough empty RX buffer descriptors to receive the number of
frames specified in the RFTHR.
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