Motorola MPC823e User Manual

PCMCIA Interface
MOTOROLA MPC823e REFERENCE MANUAL 17-15
PCMCIA INTERFACE
17
17.5.4 PCMCIA Interface General Control Register B
The PCMCIA interface general control register B (PGCRB) provides control for the IREQ
and STSCHG interrupt levels, This register also controls the PCMCIA output port signals.
When the PCMCIA controller is not operating, the CBOE and CBRESET bits can be used
to access the OP[2:3] pins as general-purpose output pins without configuring any other
PCMCIA register.
CBIRQLVL—Card B Interrupt Request Level
Only one bit of this field must be set at any given time.
CBSCHLVL—Card B STSCHG
Level
Only one bit of this field must be set at any given time.
CBDREQ—Card B DMA Request
This field defines the pin to be used as the internal DMA request to IDMA channel 2.
0x = Disable internal DMA request from Slot B.
10 = Enable IOIS16_B
as internal DMA request for Slot B.
11 = Enable SPKR
as internal DMA request for Slot B.
Bits 18–23—Reserved
These bits are reserved and must be set to 0.
PGCRB
BIT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
CBIRQLVL CBSCHLVL
RESET
— —
R/W
R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0xE4
BIT
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
CBDREQ RESERVED CBOE
CBRES
ET
RESERVED
RESET
—————
R/W
R/W R/W R/W R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0xE4
NOTE: — = Undefined.
Note: If the PCMCIA controller is programmed to enable internal DMA, then the port C
registers must not be configured to select DREQ2.

Motorola MPC823e Specifications

General

Brand	Motorola
Model	MPC823e
Category	Computer Hardware
Language	English