© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 11
Philips Semiconductors
UM10161
Volume 1 Chapter 2: Memory map
2.2 LPC2101/02/03 memory re-mapping and boot block
2.2.1 Memory map concepts and operating modes
The basic concept on the LPC2101/02/03 is that each memory area has a "natural"
location in the memory map. This is the address range for which code residing in that area
is written. The bulk of each memory space remains permanently fixed in the same
location, eliminating the need to have portions of the code designed to run in different
address ranges.
Because of the location of the interrupt vectors on the ARM7 processor (at addresses
0x0000 0000 through 0x0000 001C, as shown in Ta ble 3
below), a small portion of the
Boot Block and SRAM spaces need to be re-mapped in order to allow alternative uses of
interrupts in the different operating modes described in Ta bl e 4
. Re-mapping of the
interrupts is accomplished via the Memory Mapping Control feature (Section 3.7 “
Memory
mapping control” on page 23).
Table 2: APB peripheries and base addresses
APB peripheral Base address Peripheral name
0 0xE000 0000 Watchdog timer
1 0xE000 4000 Timer 0
2 0xE000 8000 Timer 1
3 0xE000 C000 UART0
4 0xE001 0000 UART1
5 0xE001 4000 Not used
6 0xE001 8000 Not used
7 0xE001 C000 I
2
C0
8 0xE002 0000 SPI0
9 0xE002 4000 RTC
10 0xE002 8000 GPIO
11 0xE002 C000 Pin connect block
12 0xE003 0000 Not used
13 0xE003 4000 ADC
14 - 22 0xE003 8000
0xE005 8000
Not used
23 0xE005 C000 I
2
C1
24 0xE006 0000 Not used
25 0xE006 4000 Not used
26 0xE006 8000 SSP
27 0xE006 C000
28 0xE007 0000 Timer 3
29 0xE007 4000 Timer 4
30 - 126 0xE007 8000
0xE01F 8000
Not used
127 0xE01F C000 System Control Block
To Next Page
Loading...