Philips Semiconductors
UM10161
Volume 1 Chapter 22: Supplementary information
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 277
continued >>
14.4.3 A/D Status Register (ADSTAT, ADC0: AD0CR -
0xE003 4004) . . . . . . . . . . . . . . . . . . . . . . . . 184
14.4.4 A/D Interrupt Enable Register (ADINTEN, ADC0:
AD0INTEN - 0xE003 400C) . . . . . . . . . . . . . 184
14.4.5 A/D Data Registers (ADDR0 to ADDR7, ADC0:
AD0DR0 to AD0DR7 - 0xE003 4010 to
0xE003 402C). . . . . . . . . . . . . . . . . . . . . . . . 185
14.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
14.5.1 Hardware-triggered conversion . . . . . . . . . . 186
14.5.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
14.5.3 Accuracy vs. digital receiver. . . . . . . . . . . . . 186
Chapter 15: Timer/Counter Timer0 and Timer1
15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
15.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 187
15.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
15.4 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 188
15.5 Register description . . . . . . . . . . . . . . . . . . . 188
15.5.1 Interrupt Register (IR, TIMER0: T0IR -
0xE000 4000 and TIMER1:
T1IR - 0xE000 8000) . . . . . . . . . . . . . . . . . . 190
15.5.2 Timer Control Register (TCR, TIMER0: T0TCR -
0xE000 4004 and TIMER1: T1TCR -
0xE000 8004) . . . . . . . . . . . . . . . . . . . . . . . . 190
15.5.3 Count Control Register (CTCR, TIMER0:
T0CTCR - 0xE000 4070 and TIMER1: T1TCR -
0xE000 8070) . . . . . . . . . . . . . . . . . . . . . . . . 191
15.5.4 Timer Counter (TC, TIMER0: T0TC -
0xE000 4008 and TIMER1: T1TC -
0xE000 8008) . . . . . . . . . . . . . . . . . . . . . . . . 192
15.5.5 Prescale Register (PR, TIMER0: T0PR -
0xE000 400C and TIMER1:
T1PR - 0xE000 800C) . . . . . . . . . . . . . . . . . 192
15.5.6 Prescale Counter Register (PC, TIMER0: T0PC -
0xE000 4010 and TIMER1:
T1PC - 0xE000 8010) . . . . . . . . . . . . . . . . . 192
15.5.7 Match Registers (MR0 - MR3) . . . . . . . . . . . 192
15.5.8 Match Control Register (MCR, TIMER0: T0MCR -
0xE000 4014 and TIMER1: T1MCR -
0xE000 8014). . . . . . . . . . . . . . . . . . . . . . . . 193
15.5.9 Capture Registers (CR0 - CR3) . . . . . . . . . . 194
15.5.10 Capture Control Register (CCR, TIMER0: T0CCR
- 0xE000 4028 and TIMER1: T1CCR -
0xE000 8028). . . . . . . . . . . . . . . . . . . . . . . . 194
15.5.11 External Match Register (EMR, TIMER0: T0EMR
- 0xE000 403C; and TIMER1: T1EMR -
0xE000 803C) . . . . . . . . . . . . . . . . . . . . . . . 195
15.5.12 PWM Control Register (PWMCON, TIMER0:
PWM0CON - 0xE000 4074 and TIMER1:
PWM1CON - 0xE000 8074). . . . . . . . . . . . . 196
15.5.13 Rules for single edge controlled PWM ouputs 197
15.6 Example timer operation . . . . . . . . . . . . . . . 197
15.7 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Chapter 16: Timer/Counter Timer2 and Timer3
16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
16.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 200
16.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
16.4 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 201
16.5 Register description . . . . . . . . . . . . . . . . . . . 201
16.5.1 Interrupt Register (IR TIMER2: T2IR -
0xE007 0000 and TIMER3: T3IR -
0xE007 4000) . . . . . . . . . . . . . . . . . . . . . . . . 203
16.5.2 Timer Control Register (TCR, TIMER2: T2TCR -
0xE007 0004 and TIMER3: T3TCR -
0xE007 4004) . . . . . . . . . . . . . . . . . . . . . . . . 203
16.5.3 Count Control Register (CTCR, TIMER2:
T2CTCR - 0xE007 0070 and TIMER3: T3TCR -
0xE007 4070) . . . . . . . . . . . . . . . . . . . . . . . . 204
16.5.4 Timer Counter (TC, TIMER2: T2TC -
0xE007 0008 and TIMER3: T3TC -
0xE007 4008). . . . . . . . . . . . . . . . . . . . . . . . 205
16.5.5 Prescale Register (PR, TIMER2: T2PR -
0xE007 000C and TIMER3:
T3PR - 0xE007 400C) . . . . . . . . . . . . . . . . . 205
16.5.6 Prescale Counter register (PC, TIMER2: T2PC -
0xE007 0010 and TIMER3: T3PC -
0xE007 4010). . . . . . . . . . . . . . . . . . . . . . . . 205
16.5.7 Match Registers (MR0 - MR3) . . . . . . . . . . . 205
16.5.8 Match Control Register (MCR, TIMER2: T2MCR -
0xE007 0014 and TIMER3: T3MCR -
0xE007 4014). . . . . . . . . . . . . . . . . . . . . . . . 206
16.5.9 Capture Registers (CR0 - CR3) . . . . . . . . . . 207
16.5.10 Capture Control Register (CCR, TIMER2: T2CCR
- 0xE007 0028 and TIMER3: T3CCR -
0xE007 4028). . . . . . . . . . . . . . . . . . . . . . . . 207
To Next Page
Loading...