F.
DESCRIPTION
OF
I/O COMMANDS
Blt
Device Address
Map
DMA
CONTROLLER
0
o/
1
Clear/Set mask bit of channel
0
Address
Bit
data Description
O8H
(Command-Register)
0
o/
1
Memory to memory transfer disable/enable
1
o/
1
X
Channel
0
address hold disable/enable
[n case of bit
O=O
2
o/
1
Controller enable/disable
3
o/
1
X
Normal/Compressed timing
In case of bit
O=
1
4
o/
1
Fixed/Rotating Priority
5
0
1
X
Normal write pulse
Extended write selection
In
case of bit
3=
1
DREQ sense active high/low
DACK sense active high/low
6
7
o/
1
0/1
09H
(Request-Register)
00
01
10
11
Selection of channel
0
Selection of channel
1
Selection of channel
2
Selection of channel
3
Preset/Set of request bit
2
o/
1
3-7
X
X
Selection of mask bit of channel
0
Selection of mask bit of channel
1
Selection of mask bit of channel
2
Selection of mask bit of channel
3
OAH
(Mask-Register)
00
01
10
11
o/
1
Clear/Set of mask bit
2
X
3-7
I
x
Clear/Set mask bit of channel
1
1
I
0/1
2
I
o/l
Clear/Set mask bit of channel
2
3
I
0/1
I
Clear/Set mask bit of channel
3
F-
1
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