Tandy 1400LT - DMA Control

DMA Control
~ll data transmissions between FDC and the CPU performed in the DMA mode.
Figure
4-23 shows the DMA controller and peripheral circuitry.
BDO
I
BD7 = A0 - A15
LE
- OE
0
41 DAN
IC20
-3-G -
-E
BAO
BA7
GATE4
.I
IC17 I 1 IC19
HDA
HLA
8237cs
-
BIR
BIw
@!@
-
BMW
DR2
DMACLK
RDYTODMA
BAO
- BA7
DATA
BUS
DDIR
BEN
HRQ
HLDA
cs
DMAC
IC18
m
-m
.FIERR
UEmir
DREQ2
CLK
READY
A0
I DACK2
BDO
I
BD3
BAO
BA
1
DACK2
DACK3
A16
- A19
Figure 4-23. DMA Controller and Periphenal Circuitry
4-35