IV-16.
LCD
Controller
This LCD controller supports three display devices.
1.
LCD pannel.
2.
CRT with IRGB input.
3. CRT with COMPOSITE input.
This LCD controller is compatible with the color adapter for IBM-PC.
‘
ADDRESS
---
LCDCS
GATE1
-
VRAMCS-
GATE2
CPU
CPU
Interface
The CPU interface circuit of the V6355 is shown in Figure
4-29.
Data
Bus
(DO
-
D7), IOSEL (Chip select signal), MEMSEL (VRAM chip select signal),
IOW
(I/O
write signal),
IOR
(I/O
read signal), MEMRDY (Memory request signal), and Address Bus (A0
-
A3) serve as the interface
between the CPU and the V6355.
The addressing to all I/O registers is executed by the
I/O
command of the four least significant bits (A0
-
A3)of
port addresses with a “Low” active IOSEL signal, which enables this controller like chip selecting.
~
-
A0
A1
A2
AS
-IOSEL
MEMSEL
LCDC
U
DATA DATA
RESET
RESET
CPUAEADY
Figure
4-29.
LCDC-CPU Interface
4-42
To Next Page
Loading...
