Tandy 1400LT - IV-9. ROM Control Circuit; ROM Address Decoder Circuit; ROM and Peripheral Circuitry

IV-9. ROM Control Circuit
“0” active CSRO signal is chip enable signal for ROM (@). It is decoded in the GATE2. Figure 4-14 shows the
address decoder circuit. Figure
4-15 shows the ROM and peripheral circuitry.
BAO Io
BAl
BA2
BA3
BA4
BA5
BA6
BA7
BA8
25.A8
BA9 24
BAIO 21
BA12
BA13
26
BA~I 23~~11
+5v
GATE2
A0
Ai
A2
A3
A4
.A5
.A6
A7
A9
A10
A12
A13
A18
A19
BA14
BA15
BA16
A17
Figure 4-14. ROM Address Decoder Circuit
ME83128
csm
FIR
IC15
00
01
02
03
04
05
06
07
vcc
GND
IA
19 I-
BDO
BD
1
b02
BD3
BD4
BD5
b06
BD7
Figure 4-15. ROM and Peripheral Circuitry
4-1 1