Tandy 1400LT - Page 46

Figure 4-12 RAM-3 shows the DRAM and peripheral circuitry.
ADL-
lOOSP 10 signal is generated by the IC45 (Active time delay line) and it affects Column-address-strobe timing.
(CASO, CAS1, and
a)
--
A0
A1
A2
A3
A14
A
15
A16
P
Ij. A12
74HC 157
48
1A 3Y
2A
-#=
IC40
*
74HC157
G7,A-L
I
28
38 2Y
48
1A 3Y
2A
3A 4Y I12 1
IC43 IC300 IC302
A0 A0 1
04- i
P
CAS0
CAS 1
CAS2
MREQ
-
m
MW
1
A7 - A7 - A6 A7. - DRAHP i 5
00
DO DO
03 03
I -I t
4 s 03
I
IC44 IC30 1 IC303
IC306 (305. 306)
TIMING. AODRESS
CONTROL
I
BUS CONTROLLER
- 30nemc
1
.-
.* ..
-
..
MREQ - .. *
MREQ ADL-100SP4
AOL-1OOSPlO
AOL-lOOSP4
AOL-1OOSPlO
..
..
.- 60naec
..
Figure 4-12. RAM-3
4-9