Allwinner A20 - Page 11

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 11 / 812
– Support mirror/ alpha (plane and pixel alpha) /color key
– Format conversion: ARGB 8888/4444/1555, RGB565, MONO 1/2/4/8bpp, Palette 1/2/4/8bpp (input
only), YUV 444/422/420
Memory
●
Internal BROM
– Support system boot from NAND Flash, SPI Nor Flash (SPI0), SD Card/TF card (SDC0/2)
– Support system code download through USB DRD (Dual-Role Device)
●
SDRAM
– Support DDR3/DDR3L/DDR2
– Up to 32-bit bus width
– Support 2GB address space
– 16 address signal lines and 3 bank signal lines
●
NAND Flash
– Comply to ONFI 2.3 and Toggle 1.0
– Up to 64-bit ECC per 512 bytes or 1024 bytes
– Up to 8bits data bus width
– Support 1K/2K/4K/8K/16K page size
– Up to 8 CE and 2 RB
– Support system boot from NAND flash
– Support SLC/MLC NAND and EF-NAND
– Support SDR/DDR NAND interface
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SD/MMC Interface
– Comply with eMMC standard specification V4.3
– Comply with SD physical layer specification V3.0
– Comply with SDIO card specification V2.0
– 1/4/8-bits bus width
– Support HS/DS/SDR12/SDR25 bus mode
– Support eMMC mandatory and alternative boot operations
– Support four independent SD/MMC/SDIO controllers
– Support SDSC/SDHC/SDXC/MMC/ RS-MMC card
– Support eMMC/iNand Flash
– Support 1GB/2GB/4GB/8GB/16GB/32GB/64GB /128GB SD/MMC card
– Support SDIO interrupt detection
– Support descriptor-based internal DMA controller for efficient scatter and gather operations