Allwinner A20 - Page 221

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 221 / 812
Offset: 0x00
Register Name: SS_CTL
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
010: Triple DES (3DES)
011: SHA-1
100: MD5
101: PRNG
Others: Reserved
3
/
/
/
2
R/W
0
SHA1_MD5_END_BIT
SHA-1/MD5 Data End bit
Write ‘1’ to tell SHA-1/MD5 engine that the text data is end. If
there is some data in FIFO, the engine would fetch these data
and process them. After finishing message digest, this bit is
clear to ‘0’ by hardware and message digest can be read out
from digest registers.
Notes: It is only used for SHA-1/MD5 engine.
1
R/W
0
PRNG_START
PRNG start bit
In PRNG one-shot mode, write ‘1’ to start PRNG. After
generating one group random data (5 words), this bit is clear to
‘0’ by hardware.
0
R/W
0
SS_ENABLE
SS Enable
A disable on this bit overrides any other block and flushes all
FIFOs.
0: Disable
1: Enable
1.16.4.2. SECURITY SYSTEM KEY [N] REGISTER
Offset: 0x04 +4*n
Register Name: SS_KEY[n]
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:0
R/W
0
SS_KEY
Key[n] Input Value (n= 0~7)/ PRNG Seed[n] (n= 0~5)